Generation of computers

Compare the distinctions between first, second, third, fourth and fifth generation of computers.

The first generation computers were developed during 1943-1958. It used vacuum tubes as the active electronic components and was therefore very large. However some of the features are as follows-

      a) They were extremely large and occupied a very large space.

      b) They used vacuum tubes as memory device.

c    c) They were very expensive and consumed a lot of electrical power.

      d) The operating speed was measured in milliseconds.

      e) These computers had low level of accuracy and reliability.

      f ) Storage capacity was too small only 1 to 4Kb.

      g) They used machine level programming language.

The examples are- UNIVAC, ENIAC, EDSAC, EDVAC, and UNIVAC.

The second generation computers were developed during 1959-1965. The invention of the transistor by three scientists of Bell Telephone Laboratories in 1947 greatly changed the development of computers. However some of the features are as follows-

       a) These computers used transistor.

       b) They were smaller, faster and cheaper than first generation of computer.

       c) They consumed less electrical power than first generation.

       d) The operating speed was measured in microseconds.

       e) They were more reliable and accurate than the first generation computers.

        f) They could understand high level language such as COBOL.

        g) Magnetic tapes were used as secondary storage media.

The examples are – IBM 1620, IBM 1401, and CDC 3600.

The third generation computers were developed during 1966-1973. The development of Integrated Circuit (IC) signaled the beginning of the third generation computers. However some of the features are as follows-

         a) These computers used integrated circuits.

         b) They were small, efficient and reliable.

         c) Operating systems were developed.

         d) Monitors and keyboards were introduced for input and output of data.

         e) Magnetic disks were used for secondary storage.

         f) The operating speed was measured in nano seconds.

         g) They could understand large number of high level languages.

The examples are – IBM 360, ICL -1900, and IBM 370 etc.

The fourth generation computers were developed during 1974-1990. This generation of computer is presently in use. The development of microprocessor signaled the beginning of the fourth generation of computers. However some of the features are as follows-

      a) These computers use LSI and VLSI technologies.

      b) Its sizes were reduced to desktop and laptop computer.

      c) These computers are highly reliable and accurate.

      d) They have a large memory and high functional speed.

      e) The operating speed is measured in beyond picoseconds and MIPS (Million of instruction per second)

       f) Magnetic disk is the common source of external storage.

       g) Multiprocessing and multiprogramming OS (operating system) are used.

       h) 4GL are also used.

The examples are – IBM PC, Apple/Macintosh, 8086, 80286 SX, 80386 SX etc.

The computers having artificial intelligence (AI) and high processing capacity undergoing on the development stage from 1990 are said to be fifth generation computers. However some of the features are as follows-

      a) The speed will be extremely high in fifth generation computer.

      b) These computers will be using Ultra Large Scale Integration (ULSI) technology.

       c) The goal of fifth generation computers is to develop machines that will be able to think and take decisions.

      d) It can perform large number of parallel processing.

      e) Biochips and Gallium Arsenide (GaAS) will be used as memory devices.

       f) Large uses of natural language processing and user friendly.

Able to make decisions like human beings.

How to Develop an Operating System

What is this about?

Operating systems can be a very complex topic. Learning how operating systems work can be a great learning experience.

The purpose of this series is to teach the black art of Operating System (OS) Development, from the ground up. Whether you want to make your own OS, or simply to learn how they work, this series is for you.

What is an Operating System?

An Operating System provides the basic functionality, look, and feel, for a computer. The primary purpose is to create a workable Operating Environment for the user.

An example of an Operating System is Windows, Linux, and Macintosh.

If you have never programmed before

Computer programming is designing and writing software, or programs, for the computer to load and execute. However, the Operating System needs to be designed with this functionality.

An Operating System is not a single program, but a collection of software that work and communicate with each other. This is what I mean by "Operating Environment".

Because Operating Systems are a collection of software, in order to develop an Operating System, one must know how to develop software. That is, one must know computer programming.

If you have never programmed before, take a look at the Requirements section below, and look no further. This section will have links to good tutorials and articles that could help you to learn computer programming with C++ and 80x86 Assembly Language.

Requirements

Knowledge of the C Programming Language

Using a high level language, such as C, can make OS development much easier. The most common languages that are used in OS development are C, C++, and Perl. Do not think these are the only languages that may be used; It is possible in other languages. I have even seen one with FreeBASIC! Getting higher level languages to work properly can also make it harder to work within the long run, however.

C and C++ are the most common, with C being the most used. C, as being a middle level language, provides high level constructs while still providing low level details that are closer to assembly language, and hence, the system. Because of this, using C is fairly easy in OS development. This is one of the primary reasons why it is the most commonly used: Because the C programming language was originally designed for system level and embedded software development.

Because of this, we are going to be using C for most of the OS.

C is a complex programming language, that can take a book to cover. 

Knowledge of x86 Assembly Language

80x86 Assembly Language is a low level programming language. Assembly Language provides a direct one to one relation with the processor machine instructions, which make assembly language suitable for hardware programming.

Assembly Language, as being low level, tend to be more complex and harder to develop in, then high level languages like C. Because of this, and to aid in simplicity, We are only going to use assembly language when required, and no more.

Assembly Language is another complex language that can take a book to fill. 

Getting ready
Tools of the trade

In developing low level code, we will need specialized low level software to help us out. Some of these tools are not needed, however, they are highly recommended as they can significantly aid in development.

NASM - The Assembler

The Netwide Assembler (NASM) can generate flat binary 16bit programs, while most other assemblers (Turbo Assembler (TASM), Microsoft's Macro Assembler (MASM)) cannot.

During the development of the OS, some programs must be pure binary executables. Because of this, NASM is a great choice to use.

Microsoft Visual C++ 2012

Because portability is a concern, most of the code for our operating system will be developed in C.During OS Development, there are some things that we must have control over that not all compilers may support, however. For example, say good bye to all runtime compiler support (templates, exceptions) and the good old standard library! Depending on the design of your system, you may also need to support or change more detailed properties: Such as loading at a specific address, adding your own internal sections in your programs' binary, etc..) The basic idea is that not all compilers out there are capable of developing operating system code.

I will be using Microsoft Visual C++ for developing the system. However, it is also possible to develop in other compilers such as DJGPP, GCC or even Cygwin. Cygwin is a command shell program that is designed to emulate Linux command shell. There is a GCC port for Cygwin.

Support for other compilers

As previously stated, it is possible to develop an operating system using other compilers. While my primary compiler of use will be Visual C++.

Currently, I plan on describing on setting up the environments for:

• DJGPP
• Microsoft Visual Studio 2012
• GCC
• Mingw
• Pelles 

Copying the Boot Loader

The bootloader is a pure binary program that is stored in a single 512 byte sector. It is a very important program as it is impossible to create an OS without it. It is the very first program of your OS that is loaded directly by the BIOS, and executed directly by the processor.

We can use NASM to assemble the program, but how do we get it on a floppy disk? We cannot just copy the file. Instead, we have to overwrite the boot record that Windows places (after formatting the disk) with our bootloader. Why do we need to do this? Remember that the BIOS only looks at the bootsector when finding a bootable disk. The bootsector, and the "boot record" are both in the same sector! Hence, we have to overwrite it.

There are alot of ways we can do this. Here, I will present two. If you are unable to get one method working on your system, our readers may try the other method.

Warning: Do Not attempt to play with the following software until you how to use it. Using this oftware incorrectly can corrupt the data on your disk or make your PC unable to boot.

PartCopy - Low Level Disk Copier

PartCopy allows the copying of sectors from one drive to another. PartCopy stands for "Partial copy". Its function is to copy a certain number of sectors from one location to another, to and from a specific address.

Windows DEBUG Command

Windows provides a small command line debugger that may be used through the command line. There are quite a bit of different things that we can do with this software, but all we need it to do is copy our boot loader to the first 512 bytes on disk.

Go to the command prompt, and type debug. You will be greeted by a little prompt (-):

C:\Documents and Settings\Michael>debug
-

Here is where you enter your commands. h is the help command, q is the quit command. The w (write) command is the most important for us.

You can have debug load a file into memory such as, say, our boot loader:

C:\Documents and Settings\Michael>debug boot_loader.bin
-

This allows us to perform operations on it. (We can also use debugs L (Load) command to load the file is we wanted to). In the above example,boot_loader.bin will be loaded at address 0x100.

To write the file to the first sector of our disk, we need to use the W (Write) command which takes the following form:

W [address] [drive] [firstsector] [number]

Okay... so let's see: The file is at address 0x100. We want the floppy drive (Drive 0). The first sector is the first sector on the disk (sector 0) and the number of sectors is ehm... 1.

Putting this together, this is our command to write boot_loader.bin to the boot sector of a floppy:

C:\Documents and Settings\Michael>debug boot_loader.bin
-w 100 0 0 1
-q

VFD - Virtual Floppy Drive

Weather you have a floppy drive or not, this program is very useful. It can simulate a real floppy drive from a stored floppy image, or even in RAM. This program creates a virtual floppy image, allows formatting, and copying files (Such as, your kernel perhaps?) directly using Windows Explorer.

Bochs Emulator - PC Emulator and Debugger

You pop in a floppy disk into a computer, in hopes that it works. You boot your computer and look in aw at your greatest creation! ...Until your floppy motor dies out because you forgot to send the command to the controller in your bootloader.

When working with low level code, it is possible to destroy hardware if you are not careful. Also, to test your OS, you will need to reboot your computers hundreds of times during development.

Also, what do you do if the computer just reboots? What do you do if your Kernel crashes? Because there is no debugger for your OS, it is virtually impossible to debug.

The solution? A PC Emulator. There are plenty available, two of them being VMWare and Bochs Emulator. I will be using Bochs and Microsoft Virtual PC for testing.

Thats all, fokes

If you would like to run your system on a real computer that does not have a floppy drive, it is still possible to boot from CD even though it is a floppy image. This is done through Floppy Emulation that which most of BIOSs support.

Simply get a CD burning software (I personally use MagicISO) that can create a bootable ISO from a floppy image. Then, simply burn the ISO image to a CD and it should work.

The Build Process

There are a lot of tools listed above. To better understand how they can be useful, we should take a look at the entire build process of the OS.

• Setting everything up
1. Use VFD to create and format a virtual floppy image to use.
2. Set up Bochs Emulator to boot from the floppy image.
• The bootloader
1. Assemble the bootloader with NASM to create a flat binary program.
2. Use PartCopy or the DEBUG command to copy the bootloader to the bootsector of the virtual floppy image.
• The Kernel (And basically all other programs)
1. Assembly and/or compile all sources into an object format (Such as ELF or PE) that can be loaded and executed by the boot loader.
2. Copy kernel into floppy disk using Windows Explorer.
• Test it!
1. Using Bochs emulator and debugger, using a real floppy disk, or by using MagicISO to create a bootable CD.

CPU design (part 2)

            Register Organization

There are a variety of CPU registers that are employed to control the operation of the CPU. Most of these, on most machines, are not visible to the user.

Different machines will have different register organizations and use different terminology. We will discuss here the most commonly used registers which are part of most of the machines.

Four registers are essential to instruction execution:

Program Counter (PC): Contains the address of an instruction to be fetched. Typically, the PC is updated by the CPU after each instruction fetched so that it always points to the next instruction to be executed. A branch or skip instruction will also modify the contents of the PC.

Instruction Register (IR): Contains the instruction most recently fetched. The fetched instruction is loaded into an IR, where the opcode and operand specifiers are analyzed.

Memory Address Register (MAR): Containts the address of a location of main memory from where information has to be fetched or information has to be stored. Contents of MAR is directly connected to the address bus.

Memory Buffer Register (MBR): Contains a word of data to be written to memory or the word most recently read. Contents of MBR is directly connected to the data bus.It is also known as Memory Data Register(MDR).

Apart from these specific register, we may have some temporary registers which are not visible to the user. As such, there may be temporary buffering registers at the boundary to the ALU; these registers serve as input and output registers for the ALU and exchange data with the MBR and user visible registers.

Processor Status Word All CPU designs include a register or set of registers, often known as the processor status word (PSW), that contains status information. The PSW typically contains condition codes plus other status information. Common fields or flags include the following: Sign: Contains the sign bit of the result of the last arithmatic operation. Zero: Set when the result is zero. Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a high order bit. Equal: Set if a logical campare result is equal. Overflow: Used to indicate arithmatic overflow. Interrupt enable/disable: Used to enable or disable interrupts. Supervisor: Indicate whether the CPU is executing in supervisor or user mode. Certain privileged instructions can be executed only in supervisor mode, and certain areas of memory can be accessed only in supervisor mode. Apart from these, a number of other registers related to status and control might be found in a particular CPU design. In addition to the PSW, there may be a pointer to a block of memory containing additional status information (e.g. process control blocks). Concept of Program Execution The instructions constituting a program to be executed by a computer are loaded in sequential locations in its main memory. To execute this program, the CPU fetches one instruction at a time and performs the functions specified. Instructions are fetched from successive memory locations until the execution of a branch or a jump instruction. The CPU keeps track of the address of the memory location where the next instruction is located through the use of a dedicated CPU register, referred to as the program counter (PC). After fetching an instruction, the contents of the PC are updated to point at the next instruction in sequence. For simplicity, let us assume that each instruction occupies one memory word. Therefore, execution of one instruction requires the following three steps to be performed by the CPU: Fetch the contents of the memory location pointed at by the PC. The contents of this location are interpreted as an instruction to be executed. Hence, they are stored in the instruction register (IR). Symbolically this can be written as:                            IR  = [ [PC] ]                                    Increment the contents of the PC by 1.                            PC = [PC] + 1                                   Carry out the actions specified by the instruction stored in the IR.  The first two steps are usually referred to as the fetch phase and the step 3 is known as the execution phase. Fetch cycle basically involves read the next instruction from the memory into the CPU and along with that update the  contents of the program counter. In the execution phase, it interpretes the opcode and perform the indicated operation. The instruction fetch and execution phase together known as instruction cycle. The basic instruction cycle is shown in the Figure 5.3.                                                                                                  Figure 5.3: Basic Instruction cycle In cases, where an instruction occupies more than one word, step 1 and step 2 can be repeated as many times as necessary to fetch the complete instruction. In these cases, the execution of a instruction may involve one or more operands in memory, each of which requires a memory access. Further, if indirect addressing is used, then additional memory access are required.  The fetched instruction is loaded into the instruction register. The instruction contains bits that specify the action to be performed by the processor. The processor interpretes the instruction and performs the required action. In general, the actions fall into four categories: Processor-memory: Data may be transfrred from processor to memory or from memory to processor.                              Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module.                           Data processing: The processor may perform some arithmatic or logic operation on data.                                    Control: An instruction may specify that the sequence of execution be altered. The main line of activity consists of alternating instruction fetch and instruction execution activities. After an instruction is fetched, it is examined to determine if any indirect addressing is involved. If so, the required operands are fetched using indirect addressing. The execution cycle of a perticular instruction may involve more than one reference to memory. Also, instead of  memory references, an instruction may specify an I/O operation. With these additional considerations the basic instruction cycle can be expanded with more details view in the Figure 5.4. The figure is in the form of a state diagram.

CPU design (part 1)

The operation or task that must perform by CPU are:

• Fetch Instruction: The CPU reads an instruction from memory.


• Interpret Instruction: The instruction is decoded to determine what action is required.


• Fetch Data: The execution of an instruction may require reading data from memory or I/O module.


• Process data: The execution of an instruction may require performing some arithmatic or logical operation on data.


• Write data: The result of an execution may require writing data to memory or an I/O module.

To do these tasks, it should be clear that the CPU needs to store some data temporarily. It must remember the location of the last instruction so that it can know where to get the next instruction. It needs to store instructions and data temporarily while an instruction is beign executed. In other words, the CPU needs a small internal memory. These storage location are generally referred as registers.

The major components of the CPU are an arithmatic and logic unit (ALU) and a control unit (CU). The ALU does the actual computation or processing of data. The CU controls the movement of data and instruction into and out of the CPU and controls the operation of the ALU.

The CPU is connected to the rest of the system through system bus. Through system bus, data or information gets transferred between the CPU and the other component of the system. The system bus may have three components:

Data Bus:
Data bus is used to transfer the data between main memory and CPU.
Address Bus:
Address bus is used to access a particular memory location by putting the address of the memory location.
Control Bus:
Control bus is used to provide the different control signal generated by CPU to different part of the system. As for example, memory read is a signal generated by CPU to indicate that a memory read operation has to be performed. Through control bus this signal is transferred to memory module to indicate the required operation.

There are three basic components of CPU: register bank, ALU and Control Unit. There are several data movements between these units and for that an internal CPU bus is used. Internal CPU bus is needed to transfer data between the various registers and the ALU.

Register Organization

A computer system employs a memory hierarchy. At the highest level of hierarchy, memory is faster, smaller and more expensive. Within the CPU, there is a set of registers which can be treated as a memory in the highest level of hierarchy. The registers in the CPU can be categorized into two groups:

• User-visible registers: These enables the machine - or assembly-language programmer to minimize main memory reference by optimizing use of registers.
                             
• Control and status registers: These are used by the control unit to control the operation of the CPU. Operating system programs may also use these in privileged mode to control the execution of program.

User-visible Registers:

            The user-visible registars can be categorized as follows:

• General  Purpose  Registers
• Data  Registers
• Address  Registers
• Condition  Codes

General-purpose registers can be assigned to a variety of functions by the programmer. In some cases, general- purpose registers can be used for addressing functions (e.g., register indirect, displacement).

In other cases, there is a partial or clean separation between data registers and address registers.

Data registers may be used to hold only data and cannot be employed in the calculation of an operand address.

Address registers may be somewhat general purpose, or they may be devoted to a particular addressing mode. Examples include the following:

• Segment pointer: In a machine with segment addressing, a segment register holds the address of the base of the segment. There may be multiple registers, one for the code segment and one for the data segment.
• Index registers: These are used for indexed addressing and may be autoindexed.
• Stack pointer: If there is user visible stack addressing, then typically the stack is in memory and there is a dedicated register that points to the top of the stack.

Condition Codes (also referred to as flags) are bits set by the CPU hardware as the result of the operations. For example, an arithmatic operation may produce a positive, negative, zero or overflow result. In addition to the result itself beign stored in a register or memory, a condition code is also set. The code may be subsequently be tested as part of a condition branch operation. Condition code bits are collected into one or more registers.
                                                                                             ......... to be continued   

Important UNIX Command

1. man - show manual for a command, example: man ls hit q to exit the man page.
2. cd - change directory, example: cd /etc/
3. ls - list directory, similar to dir on windows. example: ls /etc, use ls -l /etc to see more detail
4. cp - copy a file or directory, example: cp source dest if you want to copy a directory use the -R option for recursive: cp -R /source /dest
5. mv - move a file, example: mv source dest
6. rm - remove a file, example: rm somefile to remove a directory you may need the -R option, you can also use the -f option which tells it not to confirm each file: rm -Rf /dir
7. cat - concatenate, or output a file cat /var/log/messages
8. more - outputs one page of a file and pauses. example: more /var/log/messages press q to exit before getting to the bottom. You can also pipe to more | more from other commands, for example ls -l /etc | more
9. scp - secure copy, copies a file over SSH to another server. example: scp /local/file user@host.com:/path/to/save/file
10. tar - tape archiver, tar takes a bunch of files, and munges them into one.tar file, the files are often compressed with the gzip algorithm, and use the.tar.gz extension. to create a tar tar -cf archive.tar /directory, then to extract the archive to the current directory run tar -xf archive.tar to use gzip, just add a z to the options, to create a tar.gz: tar -czf archive.tar.gz /dir to extract it tar -xzf archive.tar.gz
11. grep - pattern matcher, grep takes a regular expression, or to match a simple string you can use fast grep, fgrep failure /var/log/messages, I'm usually just looking for a simple pattern so I tend to use fgrep more than regular grep.
12. find - lists files and directories recursively on a single line, I usually pipe grep into the mix when I use find, eg: find / | fgrep log
13. tail - prints the last few lines of a file, this is handy for checking log files tail /var/log/messages if you need see more lines, use the -n option, tail -n 50 /var/log/messages you can also use the -f option, which will continuously show you the end of the file as things are added to it (very handy for watching logs) tail -f /var/log/messages
14. head - same as tail, but shows the first few lines the file
15. vi - text editor, there are several text editors such as emacs, and nano, but vi is usually installed on any server so its a good one to learn. To edit a file typevi file to edit a line press Esc i then to save changes and exit use Esc wq, or to quit without saving use Esc q!. There are a million other commands, but that will enable you to edit files at a basic level.

UGC-NET OBJECTIVE MODE

1.	The UGC-NET is conducting in objective mode from June 2012 onwards. The Test will consist of three papers. All the three papers will consist of only objective type questions and will be held on the day of Examination in two separate sessions as under:
	Session Paper Number of Questions Marks Duration First I 60 out of which 50 questions are to be attempted 50x2 = 100 1¼ Hours (09.30 a.m. to 10.45 a.m.) First II 50 questions all of which are compulsory 50x2 = 100 1¼ Hours (10.45 a.m. to 12.00 Noon.) Second III 75 questions all of which are compulsory 75x2 = 150 2½ Hours (01.30 p.m. to 04.00 p.m.)
2.	The candidates are required to obtain minimum marks separately in Paper-I, Paper-II and Paper-III as given below:
	Category Minimum marks (%) to be obtained Paper-I Paper-II Paper-III General 40 (40%) 40 (40%) 75 (50%) OBC 35 (35%) 35 (35%) 67.5 (45%) rounded off to 68 PH/VH/SC/ST 35 (35%) 35 (35%) 60 (40%)
	Only such candidates who obtain the minimum required marks in each Paper, separately, as mentioned above, will be considered for final preparation of result. However, the final qualifying criteria for Junior Research Fellowship (JRF) and eligibility for Lectureship shall be decided by UGC before declaration of result.
3.	The syllabi of Paper-I, Paper-II and Paper-III will remain the same.
4.	The candidates will be allowed to carry the carbon printout of OMR Response Sheets with them on conclusion of the examination.
5.	There will be no negative marking.

for Syllubi of NET CSE PAPER  go here

                                                                                                                                          R.P

Hazards in Pipelining:

Introduction:

     Pipelining can efficiently increase the performance of a processor by overlapping execution of instructions. But the efficiency of the pipelining depends upon, how the problem encountered during the implementation of pipelining is handled. These problems are known as HAZARDS. 

Types of Hazards: 

a)  Structural Hazards (Resource Bound)
b)  Control Hazards ( Pipelining Bubbles)
c)  Data Hazards ( Data dependencies)

Structural Hazards:
During the pipelining, the overlapped execution of instructions requires pipelining of functional units and duplication of resources to allow all possible combinations of instructions in the pipeline.This type of hazards occurs when two activities require the same resource simultaneously. 

Example:
 If machine has shared a single-memory pipeline for data and instructions. As a result,when an instruction contains a data-memory reference (load-MEM), it will conflict with the instruction reference for a later instruction (instr 3-IF):
   

                            Clock cycle number 

Instr        1       2       3       4           5          6        7         8   

Load       IF    ID   EX   MEM*  WB         

Instr 1             IF   ID      EX       MEM   WB         

Instr2                     IF      ID         EX       MEM  WB    

Instr 3                              IF*       ID         EX      MEM  WB  

 To resolve this, we stall the pipeline for one clock cycle when a data-memory access occurs. The effect of the stall is actually to occupy the resources for that instruction slot. The following table shows how the stalls are actually implemented. 
 

Clock cycle number 

Instr    1  2 3 4  5 6 7 8 9  

Load  IF ID  EX MEM WB        

Instr1       IF ID   EX     MEM WB      

Instr 2           IF   ID       EX     MEM  WB       

Instr 3        stall     IF      ID      EX       MEM W B  

 

Instruction 1 assumed not to be data-memory reference (load or store), otherwise Instruction 3 cannot start execution because of structural hazard.
 We know that introduction of stall reduces the performance of the system but there are following reasons for allowing structural hazard while designing the system:
To reduce cost: For example, machines that support both an instruction and a
cache access every cycle (to prevent the structural hazard of the above example)
require at least twice as much total memory.

A classical way to avoid  hazard at memory access is by providing separate data and instruction cache

Control Hazard:
     This type of hazard is caused by uncertainty of execution path, branch taken or
not taken.It results when we branch to a new location in the program, invalidating
everything we have loaded in our pipeline. They arises from the pipelining of branches and other instruction that change the content of PC (program counter). If a branch instruction enters in the pipeline , the performance would be hampered. 

  CLK        0     1      2      3         4       5       6     7     8     9     10     11     12

 I1             IF    ID    EX    W  

 I2                     IF    ID     EX    W

 I3                             IF     ID      EX     W 

 I4                                      IF       ID      EX    W 

                                         overlapped execution without branching

I1              IF    ID     EX    W

I2                      IF      ID     EX    W 

I3                                                      IF  ID      EX    W

I4                                                             IF     ID      EX    W 

                                         overlapped execution with branching

Data Hazards:

￿  Data hazards occur when the pipeline changes the order of read/write accesses to operands so that the order differs from the order seen by sequentially executing instructions on the unpipelined machine.
￿  Data hazards are also known as data dependency. Data dependency is the condition in which the outcome of the current operation is dependent on the outcome of a previous instruction that has not yet been executed to completion because of the effect of the pipeline.
￿  Data hazards arise because of the need to preserve the order of the execution of instructions.
The following example shows the data hazards: 
          Add R2, R1, R0           [R2]     [R1] + [R0]
             
          Sub R1, R5, R6            [R4]     [R5] – [R6] 

Data hazards are classified into three types:

1.  RAW-  Read After Write      (also known as True Data Dependency)
2.  WAW- Write After Write      (also known as Output Dependency)
3.  WAR – Write After Read      (also known as Anti Data Dependency)

￿  RAW hazard is most common hazard that occurs when a read operation takes place after a write. The following example shows the possible RAW hazards: 

             Add  t1, A, B
        
             Sub   t2, t1, C

Solution: Internal forwarding (this can be used for all types of Data hazards) 

WAW hazard is the hazard that occurs when a write operation follows another write operation. This hazard is present only in pipelines that write in more than one pipe stage or allow an instruction to proceed even when a previous instruction is stalled. 
￿   This following example shows the possible WAW hazard:

                        Add  t1, A, B
         
                        Sub  t1, C,  D

Solution: The WAW hazards can be avoided by doing following changes in the pipelining:

                 -  Move write back for an ALU operation into the MEM stage , since                           ..                   the data value is available be then.    

                 -  By assuming that the data memory access takes place in 2 pipelining     .            ..                   stages. 
 
￿  WAR hazard is the hazard that occurs when write operation follows read operation.
This following example shows the possible WAR hazard:

                       Add   R1, R2, R3


                       Sub    R2, R2, R5

Solution: The WAR hazard can be avoided by internal forwarding and by modifying pipeline architecture such that consecutive Write and Read occur after few clock  cycles

MEMORY

The memory of computer is broadly categories into two categories:

• Internal and
• external

Internal memory is used by CPU to perform task and external memory is used to store bulk information, which includes large software and data.Memory is used to store the information in digital form. The memory hierarchy is given by:

• Register
• Cache Memory
• Main Memory
• Magnetic Disk
• Removable media (Magnetic tape)

Register: This is a part of Central Processor Unit, so they reside inside the CPU. The information from main memory is brought to CPU and keep the information in register. Due to space and cost constraints, we have got a limited number of registers in a CPU. These are basically faster devices. Cache Memory: Cache memory is a storage device placed in between CPU and main memory. These are semiconductor memories. These are basically fast memory device, faster than main memory. We can not have a big volume of cache memory due to its higher cost and some constraints of the CPU. Due to higher cost we can not replace the whole main memory by faster memory. Generally, the most recently used information is kept in the cache memory. It is brought from the main memory and placed in the cache memory. Now a days, we get CPU with internal cache. Main Memory: Like cache memory, main memory is also semiconductor memory. But the main memory is relatively slower memory. We have to first bring the information (whether it is data or program), to main memory. CPU can work with the information available in main memory only. Magnetic Disk: This is bulk storage device. We have to deal with huge amount of data in many application. But we don't have so much semiconductor memory to keep these information in our computer. On the other hand, semiconductor memories are volatile in nature. It loses its content once we switch off the computer. For permanent storage, we use magnetic disk. The storage capacity of magnetic disk is very high. Removable media: For different application, we use different data. It may not be possible to keep all the information in magnetic disk. So, which ever data we are not using currently, can be kept in removable media. Magnetic tape is one kind of removable medium. CD is also a removable media, which is an optical device.   Register, cache memory and main memory are internal memory. Magnetic Disk, removable media are external memory. Internal memories are semiconductor memory. Semiconductor memories are categoried as volatile memory and non-volatile memory. RAM: Random Access Memories are volatile in nature. As soon as the computer is switched off, the contents of memory are also lost. ROM: Read only memories are non volatile in nature. The storage is permanent, but it is read only memory. We can not store new information in ROM. Several types of ROM are available: PROM: Programmable Read Only Memory; it can be programmed once as per user requirements.                    EPROM: Erasable Programmable Read Only Memory; the contents of the memory can be erased and store new data into the memory. In this case, we have to erase whole information.                                   EEPROM: Electrically Erasable Programmable Read Only Memory; in this type of memory the contents of a particular location can be changed without effecting the contents of other location. The main memory of a computer is semiconductor memory. The main memory unit of computer is basically consists of two kinds of memory:      RAM : Random access memory; which is volatile in nature.  ROM : Read only memory; which is non-volatile.  The permanent information are kept in ROM and the user space is basically in RAM.The smallest unit of information is known as bit (binary digit), and in one memory cell we can store one bit of information. 8 bit together is termed as a byte. The maximum size of main memory that can be used in any computer is determined by the addressing scheme. A computer that generates 16-bit address is capable of addressing upto 216  which is equal to 64K memory location. Similarly, for 32 bit addresses, the total capacity will be 232 which is equal to 4G memory location.                                                                                   ...........to be continued

Harvard Architecture

The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data.

Contrast with other computer architectures

In a computer with the contrasting von Neumann architecture (and no cache), the CPU can be either reading an instruction or reading/writing data from/to the memory. Both cannot occur at the same time since the instructions and data use the same bus system. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without a cache. A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway.

The Modified Harvard architecture is very much like the Harvard architecture but provides a pathway between the instruction memory and the CPU that allows words from the instruction memory to be treated as read-only data. This allows constant data, particularly text strings, to be accessed without first having to be copied into data memory, thus preserving more data memory for read/write variables. Special machine language instructions are provided to read data from the instruction memory.

Internal vs. external design

Modern high performance CPU chip designs incorporate aspects of both Harvard and von Neumann architecture. On-chip cache memory is divided into an instruction cache and a data cache. Harvard architecture is used as the CPU accesses the cache. In the case of a cache miss, however, the data is retrieved from the main memory, which is not divided into separate instruction and data sections. Thus, while a von Neumann architecture is presented to the programmer, the hardware implementation gains the efficiencies of the Harvard architecture.

                                                                                                     .........................to be continued                     R.P

SOME important computer books

                                                                     
                                                          click here to download

                                                                              DBMS
           

                                                                        DBMS(solution)


                                                            SOFTWARE ENGINEERING

                                                                          AUTOMATA

                                                                        POINTER IN C


                                                                           ORACLE 9i

                       

                                                                                                                             R.P